Most processor-based systems, including multi-processor based systems, rely on interrupts to handle high priority, system devices and I/O device requirements. In a system having multiple processing units, usually, each processing unit has its own operating system kernel. Each processor unit also includes within its logical or local store (LS) or private memory, software code called interrupt handlers that define tasks required to handle interrupts.
Generally, once an interrupt occurs, that interrupt channel is “blocked” until the interrupt handler has completed processing the interrupt. It is sometimes difficult to handle interrupts that can happen anywhere on the multi-processor system, especially given that each interrupt channel is blocked during handling of a particular interrupt.
Further, in multi-processor systems, a processor can only execute code present in its own private memory. Thus, when using traditional interrupt handling techniques, each processor must have all of the interrupt handlers necessary to handle any potential interrupt stored in its private memory. From a computer architecture standpoint, this amounts to a substantial waste of space.
Other alternative arrangements such as central handling of interrupts in one SPU can create processing bottlenecks. Still other alternatives such as copying interrupt handlers to processors as needed can create long system latency periods during copying.
These three issues: space, bottlenecks, and latency periods, demand a better solution for interrupt handling on multi-processor systems, and especially on widely distributed multi-processor systems such as the CELL architecture.